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Program3
- 用 vhdl 语言设计 8 位数码扫描显示电路，显示输出数据直接在程序中给出。增加 8 个 4 位锁存器作为输出显示数据缓冲器，由外部输入8个待显示的十六进制数。-Design with vhdl language display 8-bit digital scanning circuit, display output data are given directly in the program. Increased eight 4-bit latch display data buffer
DE2_115_CAMERA
- d5m的DE2驱动Verilog HDL -d5m driven on DE2 by Verilog HDL
circular-_buf
- Circular buffer VHDl implementation
Altera_VHDL
- this is vhdl code. and, or, buffer gate code device is altera cyclone2.
NOC
- a vhdl code for an noc switch, which is a set of 3*3 array of noc switches and each switch has a buffer to store the incoming data.
fifo
- fifo buffer in vhdl, first in first out in vhdl, vhdl code
MP3-coder
- In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read t
fifo
- FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
shuangxiangbuffer
- 此程序描写的是双向缓冲器，用VHDL语言描写它的功能，供同学们参考-This program descr iption is bidirectional buffer, using VHDL language to describe its function, the reference for students
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
tx_buffer_inband
- FPGA,TX发送模块VHDL程序。-tx buffer inband VHDL
buffer_tri_state
- Buffer tristate in vhdl
PPRAM-test
- 乒乓缓存，用vhdl编写，用fpga内部ram-Ping-pong buffer, using vhdl to write,
tri_state_buffer
- Tri-State Buffer using VHDL
FIFO
- FIFO code implemented in VHDL. FIFO is nothing but first in first out data buffer Here i have implement it in VHDL
VmodCAM_Ref_HD Demo_13
- This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup. The proj